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Formal Verification student

We are offering you a great opportunity to join the Formal Verification team at the Switch IP department and be a part of the IP development for the next generation Switch.
As a student in the Formal Verification team you’ll be responsible for the verification of ASIC/VLSI of a complex IP and for the development of complex Formal Verification structures.
You will be working with Verilog, System Verilog, SVA, Perl, Python
You will become an expert verification and formal engineer.
• Student for BSc in Electrical engineering, at least 3 semesters left till graduation
• Knowledge of logical gates
• Knowledge in programming
• Good learning skills
• Problems solving skill

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Software methodology & Infrastructure student

Student for EPMI – Embedded Processor Methodology & Infrastructure team.
Be part of group that define and build the tools for all System on a chip group.
The job will include
• Write software for automation of complicated and multi discipliners flow.
• Insert new technologies to emulation system like assertions, scheduler.
• Define, write and assimilate new tools and methodologies. 1. Computer science or computer Eng.
2. Second year and up or previous knowledge in C & C++.
3. C & C++ knowledge – advantage.

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Associate Design and Verification Student

Description

Marvell Israel is searching for highly potential and motivated student to join to the professional DFT (Design for Test) team that is addressing hi-scale next generation projects. Will be asked for advanced design and verification related activities while working with the most advanced commercial Electronic Design Automation (EDA) vendors and Tools for meeting Marvell hi-end standards. Asking for high technical skills and innovative thinking, when working on advance and complex top of technology devices, infrastructure, flows and tools.

Qualifications
2nd / 3rd year student in EE (must)
• Excellent interpersonal and communication skills (must)
• Self-managed , Independent work capabilities and good learning skills (must)
• Innovative thinking (must)
• Highly technical and analytical capabilities (must)
• Knowledge with logic design and verification (advantage)
• Knowledge in programming languages Verilog, VHDL, C/C++ , TCL (advantage)
• Experience with workflow and automation infrastructure development (advantage)
• Experience with commercial Electronic Design Automation (EDA) vendors and Tools (advantage)

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Architectural Exploration and Modeling student

The requisition is for an intern position in the switching architecture group

• We are developing innovative architectures that require deep architecture exploration.

• Simulation models are the main tools for exploring new architectures, validating them in context of the device level and at system level. At device level the simulations models provide means for analysis of Architectural and uArchitectural alternatives, SW/HW tradeoffs. At system level, the simulation models enable exploring system level feature for example: network caching and dynamic load balancing algorithms.

The activity is partitioned to two stages:

• Development of simulation models and infrastructure at device level and system level (e.g. Data Center). This includes traffic generators, abstract system nodes and specific device level mechanisms and features. C/C++ knowledge is an advantage but not mandatory.

• Architecture exploration which involves running regressions of different architecture options and parameters, analysis of simulation metrics leading to recommendations for the architecture.

The intern will develop simulation models at device level and system level based on tools like C++ and SystemC. The models will be used for architecture exploration. The definition might be in different levels of details – either as a fully detailed specification that needs implementation or at higher level problem statement that requires the candidate to develop a solution.

In any case – it is expected from the candidate to fully understand the architecture being explored and the results of the simulation in order to fix/improve the solution.

Education: 3rd year student for BSC in electrical or computer engineering

Skills:

• Programming – Advantage

o C/C++, SystemC, Perl, Python scripting

• Knowledge – Advantage

o Computer architecture

o Networking

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Associate Software Engineer

Description:

Student position for scaleout storage systems research and development including system level performance investigation. The candidate will responsible for Continues Integration systems development activities as part of SW design cycle.

Qualifications:

  • Education: Third or above year student in Computer Science, Applied Mathematics or Electrical Engineering degree.
  • Strong analytical and research capabilities
  • Understanding of distributed computing and storage concepts
  • Candidate should have C / C++ programming skills
  • Knowledge of L2-L7 network layers – advantage
  • Knowledge of Python – advantage
  • Good team player, developed interpersonal and communication skills.
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Associate Chip Design Engineer

Description:
You will join to the switching chip design team which is responsible for the design in the projects. You will learn chip design tools and use it to execute the design.
Daily tasks include:
• Work with PD and ARC teams get the definition for the device and implement the needed design.
• Gain system understanding and knowledge in the switch architecture
• Ability to work with the different IP teams get there deliveries and integration guide line and implement it-

Qualifications:
• Student for Electrical engineering – B.Sc
Knowledged Verilog
– Knowledge in System Verilog – advantage
– Knowledge in TCL – advantage

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Associate Verification engineer

Description

We are offering you a great opportunity to Join  IP department and be part of the IP development for the next generation Switch.

As a student in the IP department you’ll be responsible for design and verification of ASIC/VLSI of a complex IP.

You will be working with Verilog, System Verilog, UVM, C++, Perl, Python.

You will become a design and verification engineer.

 

Qualifications

  •  2nd / 3rd year student in EE
  • Excellent interpersonal and communication skills • Knowledge with logic design and verification (advantage) • Knowledge in programming languages
  • Knowledge of logical gates
  • Knowledge in programming
  • Good learning skills
  • Problems solving skill
  • Ability to be a part of a team, working in cooperation
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