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מהנדסי חומרה

Design team manager

A Team manager in the Switch IP department manages 2-6 engineers, including their task allocations, schedule, work effectiveness, acquiring technical skills, career development, and more.

The team manager is responsible for several units or cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification environment, managing the full development flow and manage external interfaces.

The team manager is responsible for the team schedule and meeting quality for the different project milestones.

Required skills and experience:

  • 8+ years’ experience in VLSI development
  • Hands-on experience in design and verification
  • Team management experience
  • Excellent personal skills
  • Visionary and strategic
  • High motivation and desire to influence
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מהנדסי חומרה

Formal Verification Engineer

As a member of the Formal-Verification team you will participate in the FV efforts for Marvell's next generation IPs. This team is focusing on working with RTL designers, executing FV methodologies using the industry’s best FV tools.

You will be responsible to adjust the FV work to the right design, and to execute the FV plan, proving the design.

Qualifications 

• Familiar and capable of logic reasoning

• Knowledge of FV practice

• Ability to lead (technical wise) FV methodologies

• Ability to work independently with logic designer

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מהנדסי חומרה

Senior Asic Design and Verification Engineer

Description

Emerging SoC Technologies and Markets department is responsible for the development of NVMf technology for next generation of networking storage products.

Team had been working on the 1st NVMf generation, ownership include architecture, definition and implementation of cores IPs – RDMA and NVU.

we are Seeking an experienced ASIC Verification Engineer with proven analytical and technical skills for verification of next generation storage networking ASICs. This is an excellent opportunity to be part of an startup-like team with big company umbrella.

RESPONSIBILITIES

  • Design Micro-architecture & Documentation
  • Verification Micro-architecture & Documentation
  • Verification environment, coding, and test writing
  • System testing and debug using FPGAs is an advantage
  • Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
  • Scripting

Qualifications

  • 5-10 years’ experience in verification of networking ASICs
  • Strong communication skills, both verbal and written
  • Proficiency with Verilog & System Verilog
  • Proficiency with UVM strongly desired
  • Experience in architecting test bench environments for unit and system level verification
  • Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe
  • Proven track record with writing detailed test plans
  • Problem solving skills and out-of-the-box thinking to test and validate RTL
  • Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
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מהנדסי חומרה

Senior Architect Engineer

Description

Marvell  is Looking for an architect position to focus on physical layer aspects of switching systems. Responsible of the definition of the products architecture (HW, FW,SW) to address high speed interconnect, 802.3 L1/L2 and system level design aspects (thermal, mechanical, bom)
Qualifications
deep understanding of very high speed interconnect interfaces (SERDES) broad understanding of switching systems design in terms of power, thermal, signal integrity mechanics , build of material and cost Need to be very knowledgeable in Ethernet standards IEEE802.3

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מהנדסי חומרה

Chip Design Technical leader

Description

Marvell Israel is searching Experience design engineer for unit and top level design and infrastructures development and lead.  Joining to the professional (Design for Test) team that is addressing hi-scale next generation projects and infrastructure on advanced DFT, Clocks, Reset, Power areas.
Working with the most advanced design flows, commercial Electronic Design Automation (EDA) and in-house design infrastructure for meeting Marvell hi-end ATPG requirements.  Asking for high technical skills and experience with design flows and timing/sdc/lint/power aspects , innovative thinking, excellent interpersonal skills and leading abilities when working on advance and complex top of technology devices and infrastructure/flows/tools.
Responsibilities will include:
– Advanced Top and IP design definition , implementation and leading
– DFT, Power, Area and Timing  design and infrastructure development
– Technical design lead for end to end solution with variant work interfaces
Qualifications
• BsC  in Electrical Engineering
• 8+ Years’ experience  in Logic Design and related aspects (SDC, Power ,Clocks & Resets)
• Proven independent design experience  with IP/Chip design logic
• Design to Backend implementation (synthesis , place and route)
• High level problem solving skills
• Technical leading abilities
• Excellent interpersonal and communication  skills
• Power, DFT (Design for Test) and ATPG experience – an advantage
• Experience with infrastructure development – an advantage

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מהנדסי חומרה

IP Engineering Program Manager

Description

Marvell Networking is cutting edge silicon technology team, delivering some of the most complex products in the semiconductor industry.
We’re looking for a person that will join our team and be directly responsible for flawless delivery of complex analog IPs and new package technologies into our various Networking products.
You will own the IP program from definition to production, driving and coordinating between IP vendors, technical experts within the team, architecture team, program execution team & operations.
You will manage the communication with the IP vendor – bringing SoWs & special NDAs to completion, overlooking schedule and quality of delivery – making sure vendors meet their commitment on time.
You will make tradeoffs, resolve conflicts, mitigate risks, challenge & push the team to deliver best possible products.
Qualifications
3-5 years of technical project/program management in chip/analog development
Outstanding communication and presentation skills
Strong technical proficiency with lot of chip flow background mainly in physical & post silicon
Technical knowledge in circuit & package
Deep understanding in managing IP vendors delivery
Independent and Self-directed
Education – BSc in Electrical Engineering

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מהנדסי חומרה

Senior Design and Verification Engineer

Description

The engineer will take ownership over a unit or several units. He will do unit level design and verification and will plan and execute the verification. He will also participate in the cluster level verification.

The engineer will work with architects to understand and influence the unit architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until quality criteria is met.

Qualifications

  • Electrical engineering B.Sc graduate
  • Design RTL experience in Verilog or SV
  • Verification experience in SV, UVM, perl,
  • Knowledge in programming
  • Good learning skills
  • Problems solving skill
  • Ability to be a part of a team, working in cooperation
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מהנדסי חומרה

Verification Infrastructure and Methodologies

Description

Marvell Israel is searching for ASIC Verification and DA Engineer to join the infrastructure and methodology team.

The infrastructure and methodology team is a central supporting team that focus on developing tools and methodologies for frontend verification for all switches and controller project MISL-Design teams.

The group define, develop and supports tools for design/verification model integration, configuration management and build and run infrastructure tools. The team also supports and integrates industry standard EDA tools to complement the self-developed tools.

The team is involved both in Pre Silicon Design/Verification/Integration and infrastructures as well as Emulation flows.

The Engineer will be working on industry top of technology devices in all terms and requirements in a multi-disciplinary team of experts.

Job requires high technical skills and innovative thinking.

Responsibilities will include:

– Working closely with commercial Electronic Design Automation (EDA) vendors and Tools.

– Defining the Verification flows and mode of work and developing tools to enable them.

– Writing various scripts and tools in TCL, PERL and other languages

– Working closely with both the Design and verification teams to enable faster time to market and easier debug solutions.

implementing and supporting Build and run flows for Verification and Design

Qualifications

  • Sc. or higher in Computer Science / Computer Engineering or Electrical Engineering with 5 years or more expireance.
  • Strong programming background
  • Advantage: Experience in VLSI Design or Verification
  • Advantage: Experience in CAD and scripting
  • Ability to work independently
  • Ability and desire to learn
  • Flexible in changing tasks and priorities environment
  • Good in team work and working with many teams and groups

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מהנדסי חומרה

Verification Technical leader

Description  

•Design Micro-architecture & Documentation
• Verification Micro-architecture & Documentation
• Verification environment, coding, and test writing
• System testing and debug using FPGAs is an advantage
• Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
• Scripting
Qualifications
• 7 or more years’ experience in verification of networking ASICs
•Strong communication skills, both verbal and written
• Proficiency with Verilog & System Verilog
• Proficiency with UVM strongly desired
• Experience in architecting test bench environments for unit and system level verification
• Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe
• Proven track record with writing detailed test plans
• Problem solving skills and out-of-the-box thinking to test and validate RTL
• Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis

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מהנדסי חומרה

Design Engineer

Description

• Work with Product Definition and Architecture teams to get the device definition.

• Own and write the micro-Architecture and implement the needed design.

• End to end responsibility for the chip design.

• Tight work with the different IP teams, receive deliveries & integration guide line and implement it

• Gain system understanding and knowledge in Marvell’s switch architecture

• Learning MISL design and integration tools and use it for chip integration and macro partitioning

• Ability to support the BE team with timing analysis, floorplan guideline adjustments and reviews.

Technical knowledge:

• Experience in IP or Full chip design of at least 5 to 8 years

• Knowledge in Verilog and System Verilog

• Technical knowledge in ASIC design flow and Fullchip micro-architecture aspects

• System view oriented – capable to see the full picture

• Integration experience – advantage

• Good understanding the switching packet walk through – advantage

• I/O and package knowledge – advantage

Personal skills:

• Complex situation handling – time management and priority management

• Team work oriented – Communicative, shares his knowledge and willing to learn from others;

• Good inter-personal relation and working relation in a team

• Independent Quality driven – understands the definition, drive high quality and ability for self-check

• Stability – willing to invest for long period.

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