בואו לעבוד איתנובואו למצוא את המשרה שתתאים לכישוריכם האישיים ולשאיפות המקצועיות שלכם
Software methodology & Infrastructure student
Student for EPMI – Embedded Processor Methodology & Infrastructure team.
Be part of group that define and build the tools for all System on a chip group.
The job will include
• Write software for automation of complicated and multi discipliners flow.
• Insert new technologies to emulation system like assertions, scheduler.
• Define, write and assimilate new tools and methodologies. 1. Computer science or computer Eng.
2. Second year and up or previous knowledge in C & C++.
3. C & C++ knowledge – advantage.
Design team manager
A Team manager in the Switch IP department manages 2-6 engineers, including their task allocations, schedule, work effectiveness, acquiring technical skills, career development, and more.
The team manager is responsible for several units or cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification environment, managing the full development flow and manage external interfaces.
The team manager is responsible for the team schedule and meeting quality for the different project milestones.
Required skills and experience:
- 8+ years’ experience in VLSI development
- Hands-on experience in design and verification
- Team management experience
- Excellent personal skills
- Visionary and strategic
- High motivation and desire to influence
Formal Verification Engineer
As a member of the Formal-Verification team you will participate in the FV efforts for Marvell's next generation IPs. This team is focusing on working with RTL designers, executing FV methodologies using the industry’s best FV tools.
You will be responsible to adjust the FV work to the right design, and to execute the FV plan, proving the design.
• Familiar and capable of logic reasoning
• Knowledge of FV practice
• Ability to lead (technical wise) FV methodologies
• Ability to work independently with logic designer
Senior Architect Engineer
Marvell is Looking for an architect position to focus on physical layer aspects of switching systems. Responsible of the definition of the products architecture (HW, FW,SW) to address high speed interconnect, 802.3 L1/L2 and system level design aspects (thermal, mechanical, bom)
deep understanding of very high speed interconnect interfaces (SERDES) broad understanding of switching systems design in terms of power, thermal, signal integrity mechanics , build of material and cost Need to be very knowledgeable in Ethernet standards IEEE802.3
Senior Asic Design and Verification Engineer
Emerging SoC Technologies and Markets department is responsible for the development of NVMf technology for next generation of networking storage products.
Team had been working on the 1st NVMf generation, ownership include architecture, definition and implementation of cores IPs – RDMA and NVU.
we are Seeking an experienced ASIC Verification Engineer with proven analytical and technical skills for verification of next generation storage networking ASICs. This is an excellent opportunity to be part of an startup-like team with big company umbrella.
- Design Micro-architecture & Documentation
- Verification Micro-architecture & Documentation
- Verification environment, coding, and test writing
- System testing and debug using FPGAs is an advantage
- Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
- 5-10 years’ experience in verification of networking ASICs
- Strong communication skills, both verbal and written
- Proficiency with Verilog & System Verilog
- Proficiency with UVM strongly desired
- Experience in architecting test bench environments for unit and system level verification
- Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe
- Proven track record with writing detailed test plans
- Problem solving skills and out-of-the-box thinking to test and validate RTL
- Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
Chip Design Technical leader
Marvell Israel is searching Experience design engineer for unit and top level design and infrastructures development and lead. Joining to the professional (Design for Test) team that is addressing hi-scale next generation projects and infrastructure on advanced DFT, Clocks, Reset, Power areas.
Working with the most advanced design flows, commercial Electronic Design Automation (EDA) and in-house design infrastructure for meeting Marvell hi-end ATPG requirements. Asking for high technical skills and experience with design flows and timing/sdc/lint/power aspects , innovative thinking, excellent interpersonal skills and leading abilities when working on advance and complex top of technology devices and infrastructure/flows/tools.
Responsibilities will include:
– Advanced Top and IP design definition , implementation and leading
– DFT, Power, Area and Timing design and infrastructure development
– Technical design lead for end to end solution with variant work interfaces
• BsC in Electrical Engineering
• 8+ Years’ experience in Logic Design and related aspects (SDC, Power ,Clocks & Resets)
• Proven independent design experience with IP/Chip design logic
• Design to Backend implementation (synthesis , place and route)
• High level problem solving skills
• Technical leading abilities
• Excellent interpersonal and communication skills
• Power, DFT (Design for Test) and ATPG experience – an advantage
• Experience with infrastructure development – an advantage
IP Engineering Program Manager
Marvell Networking is cutting edge silicon technology team, delivering some of the most complex products in the semiconductor industry.
We’re looking for a person that will join our team and be directly responsible for flawless delivery of complex analog IPs and new package technologies into our various Networking products.
You will own the IP program from definition to production, driving and coordinating between IP vendors, technical experts within the team, architecture team, program execution team & operations.
You will manage the communication with the IP vendor – bringing SoWs & special NDAs to completion, overlooking schedule and quality of delivery – making sure vendors meet their commitment on time.
You will make tradeoffs, resolve conflicts, mitigate risks, challenge & push the team to deliver best possible products.
3-5 years of technical project/program management in chip/analog development
Outstanding communication and presentation skills
Strong technical proficiency with lot of chip flow background mainly in physical & post silicon
Technical knowledge in circuit & package
Deep understanding in managing IP vendors delivery
Independent and Self-directed
Education – BSc in Electrical Engineering
Associate Design and Verification Student
Marvell Israel is searching for highly potential and motivated student to join to the professional DFT (Design for Test) team that is addressing hi-scale next generation projects. Will be asked for advanced design and verification related activities while working with the most advanced commercial Electronic Design Automation (EDA) vendors and Tools for meeting Marvell hi-end standards. Asking for high technical skills and innovative thinking, when working on advance and complex top of technology devices, infrastructure, flows and tools.
2nd / 3rd year student in EE (must)
• Excellent interpersonal and communication skills (must)
• Self-managed , Independent work capabilities and good learning skills (must)
• Innovative thinking (must)
• Highly technical and analytical capabilities (must)
• Knowledge with logic design and verification (advantage)
• Knowledge in programming languages Verilog, VHDL, C/C++ , TCL (advantage)
• Experience with workflow and automation infrastructure development (advantage)
• Experience with commercial Electronic Design Automation (EDA) vendors and Tools (advantage)
Senior Design and Verification Engineer
The engineer will take ownership over a unit or several units. He will do unit level design and verification and will plan and execute the verification. He will also participate in the cluster level verification.
The engineer will work with architects to understand and influence the unit architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until quality criteria is met.
- Electrical engineering B.Sc graduate
- Design RTL experience in Verilog or SV
- Verification experience in SV, UVM, perl,
- Knowledge in programming
- Good learning skills
- Problems solving skill
- Ability to be a part of a team, working in cooperation
Architectural Exploration and Modeling student
The requisition is for an intern position in the switching architecture group
• We are developing innovative architectures that require deep architecture exploration.
• Simulation models are the main tools for exploring new architectures, validating them in context of the device level and at system level. At device level the simulations models provide means for analysis of Architectural and uArchitectural alternatives, SW/HW tradeoffs. At system level, the simulation models enable exploring system level feature for example: network caching and dynamic load balancing algorithms.
The activity is partitioned to two stages:
• Development of simulation models and infrastructure at device level and system level (e.g. Data Center). This includes traffic generators, abstract system nodes and specific device level mechanisms and features. C/C++ knowledge is an advantage but not mandatory.
• Architecture exploration which involves running regressions of different architecture options and parameters, analysis of simulation metrics leading to recommendations for the architecture.
The intern will develop simulation models at device level and system level based on tools like C++ and SystemC. The models will be used for architecture exploration. The definition might be in different levels of details – either as a fully detailed specification that needs implementation or at higher level problem statement that requires the candidate to develop a solution.
In any case – it is expected from the candidate to fully understand the architecture being explored and the results of the simulation in order to fix/improve the solution.
Education: 3rd year student for BSC in electrical or computer engineering
• Programming – Advantage
o C/C++, SystemC, Perl, Python scripting
• Knowledge – Advantage
o Computer architecture
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