בואו לעבוד איתנובואו למצוא את המשרה שתתאים לכישוריכם האישיים ולשאיפות המקצועיות שלכם
Software methodology & Infrastructure student
Student for EPMI – Embedded Processor Methodology & Infrastructure team.
Be part of group that define and build the tools for all System on a chip group.
The job will include
• Write software for automation of complicated and multi discipliners flow.
• Insert new technologies to emulation system like assertions, scheduler.
• Define, write and assimilate new tools and methodologies. 1. Computer science or computer Eng.
2. Second year and up or previous knowledge in C & C++.
3. C & C++ knowledge – advantage.
Formal Verification Engineer
As a member of the Formal-Verification team you will participate in the FV efforts for Marvell's next generation IPs. This team is focusing on working with RTL designers, executing FV methodologies using the industry’s best FV tools.
You will be responsible to adjust the FV work to the right design, and to execute the FV plan, proving the design.
• Familiar and capable of logic reasoning
• Knowledge of FV practice
• Ability to lead (technical wise) FV methodologies
• Ability to work independently with logic designer
IP Engineering Program Manager
Marvell Networking is cutting edge silicon technology team, delivering some of the most complex products in the semiconductor industry.
We’re looking for a person that will join our team and be directly responsible for flawless delivery of complex analog IPs and new package technologies into our various Networking products.
You will own the IP program from definition to production, driving and coordinating between IP vendors, technical experts within the team, architecture team, program execution team & operations.
You will manage the communication with the IP vendor – bringing SoWs & special NDAs to completion, overlooking schedule and quality of delivery – making sure vendors meet their commitment on time.
You will make tradeoffs, resolve conflicts, mitigate risks, challenge & push the team to deliver best possible products.
3-5 years of technical project/program management in chip/analog development
Outstanding communication and presentation skills
Strong technical proficiency with lot of chip flow background mainly in physical & post silicon
Technical knowledge in circuit & package
Deep understanding in managing IP vendors delivery
Independent and Self-directed
Education – BSc in Electrical Engineering
Associate Design and Verification Student
Marvell Israel is searching for highly potential and motivated student to join to the professional DFT (Design for Test) team that is addressing hi-scale next generation projects. Will be asked for advanced design and verification related activities while working with the most advanced commercial Electronic Design Automation (EDA) vendors and Tools for meeting Marvell hi-end standards. Asking for high technical skills and innovative thinking, when working on advance and complex top of technology devices, infrastructure, flows and tools.
2nd / 3rd year student in EE (must)
• Excellent interpersonal and communication skills (must)
• Self-managed , Independent work capabilities and good learning skills (must)
• Innovative thinking (must)
• Highly technical and analytical capabilities (must)
• Knowledge with logic design and verification (advantage)
• Knowledge in programming languages Verilog, VHDL, C/C++ , TCL (advantage)
• Experience with workflow and automation infrastructure development (advantage)
• Experience with commercial Electronic Design Automation (EDA) vendors and Tools (advantage)
Architectural Exploration and Modeling student
The requisition is for an intern position in the switching architecture group
• We are developing innovative architectures that require deep architecture exploration.
• Simulation models are the main tools for exploring new architectures, validating them in context of the device level and at system level. At device level the simulations models provide means for analysis of Architectural and uArchitectural alternatives, SW/HW tradeoffs. At system level, the simulation models enable exploring system level feature for example: network caching and dynamic load balancing algorithms.
The activity is partitioned to two stages:
• Development of simulation models and infrastructure at device level and system level (e.g. Data Center). This includes traffic generators, abstract system nodes and specific device level mechanisms and features. C/C++ knowledge is an advantage but not mandatory.
• Architecture exploration which involves running regressions of different architecture options and parameters, analysis of simulation metrics leading to recommendations for the architecture.
The intern will develop simulation models at device level and system level based on tools like C++ and SystemC. The models will be used for architecture exploration. The definition might be in different levels of details – either as a fully detailed specification that needs implementation or at higher level problem statement that requires the candidate to develop a solution.
In any case – it is expected from the candidate to fully understand the architecture being explored and the results of the simulation in order to fix/improve the solution.
Education: 3rd year student for BSC in electrical or computer engineering
• Programming – Advantage
o C/C++, SystemC, Perl, Python scripting
• Knowledge – Advantage
o Computer architecture
Verification Infrastructure and Methodologies
Marvell Israel is searching for ASIC Verification and DA Engineer to join the infrastructure and methodology team.
The infrastructure and methodology team is a central supporting team that focus on developing tools and methodologies for frontend verification for all switches and controller project MISL-Design teams.
The group define, develop and supports tools for design/verification model integration, configuration management and build and run infrastructure tools. The team also supports and integrates industry standard EDA tools to complement the self-developed tools.
The team is involved both in Pre Silicon Design/Verification/Integration and infrastructures as well as Emulation flows.
The Engineer will be working on industry top of technology devices in all terms and requirements in a multi-disciplinary team of experts.
Job requires high technical skills and innovative thinking.
Responsibilities will include:
– Working closely with commercial Electronic Design Automation (EDA) vendors and Tools.
– Defining the Verification flows and mode of work and developing tools to enable them.
– Writing various scripts and tools in TCL, PERL and other languages
– Working closely with both the Design and verification teams to enable faster time to market and easier debug solutions.
implementing and supporting Build and run flows for Verification and Design
- Sc. or higher in Computer Science / Computer Engineering or Electrical Engineering with 5 years or more expireance.
- Strong programming background
- Advantage: Experience in VLSI Design or Verification
- Advantage: Experience in CAD and scripting
- Ability to work independently
- Ability and desire to learn
- Flexible in changing tasks and priorities environment
- Good in team work and working with many teams and groups
Associate Software Engineer
Student position for scaleout storage systems research and development including system level performance investigation. The candidate will responsible for Continues Integration systems development activities as part of SW design cycle.
- Education: Third or above year student in Computer Science, Applied Mathematics or Electrical Engineering degree.
- Strong analytical and research capabilities
- Understanding of distributed computing and storage concepts
- Candidate should have C / C++ programming skills
- Knowledge of L2-L7 network layers – advantage
- Knowledge of Python – advantage
- Good team player, developed interpersonal and communication skills.
Associate Chip Design Engineer
You will join to the switching chip design team which is responsible for the design in the projects. You will learn chip design tools and use it to execute the design.
Daily tasks include:
• Work with PD and ARC teams get the definition for the device and implement the needed design.
• Gain system understanding and knowledge in the switch architecture
• Ability to work with the different IP teams get there deliveries and integration guide line and implement it-
• Student for Electrical engineering – B.Sc
– Knowledge in System Verilog – advantage
– Knowledge in TCL – advantage
Associate Verification engineer
We are offering you a great opportunity to Join IP department and be part of the IP development for the next generation Switch.
As a student in the IP department you’ll be responsible for design and verification of ASIC/VLSI of a complex IP.
You will be working with Verilog, System Verilog, UVM, C++, Perl, Python.
You will become a design and verification engineer.
- 2nd / 3rd year student in EE
- Excellent interpersonal and communication skills • Knowledge with logic design and verification (advantage) • Knowledge in programming languages
- Knowledge of logical gates
- Knowledge in programming
- Good learning skills
- Problems solving skill
- Ability to be a part of a team, working in cooperation
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