בואו לעבוד איתנובואו למצוא את המשרה שתתאים לכישוריכם האישיים ולשאיפות המקצועיות שלכם
Formal Verification Engineer
As a member of the Formal-Verification team you will participate in the FV efforts for Marvell's next generation IPs. This team is focusing on working with RTL designers, executing FV methodologies using the industry’s best FV tools.
You will be responsible to adjust the FV work to the right design, and to execute the FV plan, proving the design.
• Familiar and capable of logic reasoning
• Knowledge of FV practice
• Ability to lead (technical wise) FV methodologies
• Ability to work independently with logic designer
Associate Backend engineer
Marvell Israel is looking for a talented EE/CS student to join the switching department. As a member of the team, you will be responsible for implementing the future devices of routing, using the most challenging, cutting-edge technology. In this role, you will be working with industry-standard tools on the biggest, most complex ASICs the semiconductor industry has to offer
.• Electrical Engineering or Computer Science 3rd/4th year student in a reputable university
• Basic knowledge of switching devices is an advantage
Senior Asic Design and Verification Engineer-171925
Emerging SoC Technologies and Markets department is responsible for the development of NVMf technology for next generation of networking storage products.
Team had been working on the 1st NVMf generation, ownership include architecture, definition and implementation of cores IPs – RDMA and NVU.
we are Seeking an experienced ASIC Verification Engineer with proven analytical and technical skills for verification of next generation storage networking ASICs. This is an excellent opportunity to be part of an startup-like team with big company umbrella.
- Design Micro-architecture & Documentation
- Verification Micro-architecture & Documentation
- Verification environment, coding, and test writing
- System testing and debug using FPGAs is an advantage
- Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
- 5-10 years’ experience in verification of networking ASICs
- Strong communication skills, both verbal and written
- Proficiency with Verilog & System Verilog
- Proficiency with UVM strongly desired
- Experience in architecting test bench environments for unit and system level verification
- Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe
- Proven track record with writing detailed test plans
- Problem solving skills and out-of-the-box thinking to test and validate RTL
- Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
Senior Architect Engineer-180284
Marvell is Looking for an architect position to focus on physical layer aspects of switching systems. Responsible of the definition of the products architecture (HW, FW,SW) to address high speed interconnect, 802.3 L1/L2 and system level design aspects (thermal, mechanical, bom)
deep understanding of very high speed interconnect interfaces (SERDES) broad understanding of switching systems design in terms of power, thermal, signal integrity mechanics , build of material and cost Need to be very knowledgeable in Ethernet standards IEEE802.3
Chip Design Technical leader-180123
Marvell Israel is searching Experience design engineer for unit and top level design and infrastructures development and lead. Joining to the professional (Design for Test) team that is addressing hi-scale next generation projects and infrastructure on advanced DFT, Clocks, Reset, Power areas.
Working with the most advanced design flows, commercial Electronic Design Automation (EDA) and in-house design infrastructure for meeting Marvell hi-end ATPG requirements. Asking for high technical skills and experience with design flows and timing/sdc/lint/power aspects , innovative thinking, excellent interpersonal skills and leading abilities when working on advance and complex top of technology devices and infrastructure/flows/tools.
Responsibilities will include:
– Advanced Top and IP design definition , implementation and leading
– DFT, Power, Area and Timing design and infrastructure development
– Technical design lead for end to end solution with variant work interfaces
• BsC in Electrical Engineering
• 8+ Years’ experience in Logic Design and related aspects (SDC, Power ,Clocks & Resets)
• Proven independent design experience with IP/Chip design logic
• Design to Backend implementation (synthesis , place and route)
• High level problem solving skills
• Technical leading abilities
• Excellent interpersonal and communication skills
• Power, DFT (Design for Test) and ATPG experience – an advantage
• Experience with infrastructure development – an advantage
IP Engineering Program Manager-180097
Marvell Networking is cutting edge silicon technology team, delivering some of the most complex products in the semiconductor industry.
We’re looking for a person that will join our team and be directly responsible for flawless delivery of complex analog IPs and new package technologies into our various Networking products.
You will own the IP program from definition to production, driving and coordinating between IP vendors, technical experts within the team, architecture team, program execution team & operations.
You will manage the communication with the IP vendor – bringing SoWs & special NDAs to completion, overlooking schedule and quality of delivery – making sure vendors meet their commitment on time.
You will make tradeoffs, resolve conflicts, mitigate risks, challenge & push the team to deliver best possible products.
3-5 years of technical project/program management in chip/analog development
Outstanding communication and presentation skills
Strong technical proficiency with lot of chip flow background mainly in physical & post silicon
Technical knowledge in circuit & package
Deep understanding in managing IP vendors delivery
Independent and Self-directed
Education – BSc in Electrical Engineering
Associate Design and Verification Student
Marvell Israel is searching for highly potential and motivated student to join to the professional DFT (Design for Test) team that is addressing hi-scale next generation projects. Will be asked for advanced design and verification related activities while working with the most advanced commercial Electronic Design Automation (EDA) vendors and Tools for meeting Marvell hi-end standards. Asking for high technical skills and innovative thinking, when working on advance and complex top of technology devices, infrastructure, flows and tools.
2nd / 3rd year student in EE (must)
• Excellent interpersonal and communication skills (must)
• Self-managed , Independent work capabilities and good learning skills (must)
• Innovative thinking (must)
• Highly technical and analytical capabilities (must)
• Knowledge with logic design and verification (advantage)
• Knowledge in programming languages Verilog, VHDL, C/C++ , TCL (advantage)
• Experience with workflow and automation infrastructure development (advantage)
• Experience with commercial Electronic Design Automation (EDA) vendors and Tools (advantage)
Senior Design and Verification Engineer-171438
The engineer will take ownership over a unit or several units. He will do unit level design and verification and will plan and execute the verification. He will also participate in the cluster level verification.
The engineer will work with architects to understand and influence the unit architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until quality criteria is met.
- Electrical engineering B.Sc graduate
- Design RTL experience in Verilog or SV
- Verification experience in SV, UVM, perl,
- Knowledge in programming
- Good learning skills
- Problems solving skill
- Ability to be a part of a team, working in cooperation
Verification Technical leader-171155
•Design Micro-architecture & Documentation
• Verification Micro-architecture & Documentation
• Verification environment, coding, and test writing
• System testing and debug using FPGAs is an advantage
• Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
• 7 or more years’ experience in verification of networking ASICs
•Strong communication skills, both verbal and written
• Proficiency with Verilog & System Verilog
• Proficiency with UVM strongly desired
• Experience in architecting test bench environments for unit and system level verification
• Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe
• Proven track record with writing detailed test plans
• Problem solving skills and out-of-the-box thinking to test and validate RTL
• Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
Embedded development engineer
The new developer will be part of the MTS (Marvell Total Solution) group.
MTS group work on a full SW solution for L2+ products for our customers.
We are developing all SW layers working on Marvell HW modules.
• Be involved in a key position writing SW for MTS products
• Design and coding, in C.
• Develop & support new Infrastructure & tools for the MTS group developers
• Linux experience – preferred
• SW/HW engineer (in computer science Or electrical engineering)
• Skilled Developer in ANSI-C – Must.
• Networking – Advantage.
• Linux – Advantage
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