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Formal Verification student

We are offering you a great opportunity to join the Formal Verification team at the Switch IP department and be a part of the IP development for the next generation Switch.
As a student in the Formal Verification team you’ll be responsible for the verification of ASIC/VLSI of a complex IP and for the development of complex Formal Verification structures.
You will be working with Verilog, System Verilog, SVA, Perl, Python
You will become an expert verification and formal engineer.
• Student for BSc in Electrical engineering, at least 3 semesters left till graduation
• Knowledge of logical gates
• Knowledge in programming
• Good learning skills
• Problems solving skill

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מהנדסי חומרה

Software/Firmware Engineering

Role & responsibilities

• Develop software and firmware for Marvell’s next generation industry leading networking and storage devices.

• Work as part of dynamic, open-minded, innovative software team.

• Design, develop and support a feature-rich software for extremely sophisticated multiprocessor devices, including cutting-edge networking protocols.

• The job requires very strong software engineering skills, broad system understanding, and the ability to come up with creative and original solutions.

The job involves a tight interface with system architecture, OS drivers and hardware teams.

Requirements

MUST HAVE:

• B.Sc / M.Sc in Computer Science, Electrical Engineering or Computer Engineering (with honors), with 2+ years of related experience.

• At least 2 years of experience in designing, implementing and debugging software for RT embedded systems.

• Experience in C language programing.

PREFERRED:

• Experience in C++ language programing.

• RDMA and networking protocols knowledge.

• Understanding of computer/server architecture.

MUST HAVE:

• An effective interpersonal, teamwork, and communication skills.

• Excellent communication skills to interface internally and externally with all levels of the organization and to participate in problem solving and quality improvement activities.

• Demonstrates good analysis and problem-solving skills.

• Has an inherent sense of urgency and accountability.

• Grounded, detail-oriented, always backs up ideas with facts.

• Must demonstrate results in a fast-paced, multi-tasking, hands-on work environment along with superb written and verbal communication skills.

Ramat-Gan

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מהנדסי חומרה

VLSI Design Engineer

Member of the design team that is responsible for developing complex, state of the art high-speed Ethernet controller chips.

The candidate will own tasks such as micro-architecture, design, integration and other tasks as part of the chip development and testing processes.Member of the design team that is responsible for developing complex, state of the art high-speed Ethernet controller chips.

The candidate will own tasks such as micro-architecture, design, integration and other tasks as part of the chip development and testing processes.

Must have:

  • BSc. / MSc. university degree in EE/CS, graduation with honors.
  • 5+ years of experience in VLSI design.
  • Deep knowledge in Verilog.
  • Experience in micro-architecture and design of complex blocks.
  • Familiar with the verification process of a block (test plan, coverage, etc.).
  • Excellent communication skills in English (written and verbal).

Not a must, but an advantage:

  • Knowledge in networking and networking chips.
  • Experience with multi-clock domain designs.
  • Script knowledge (TCL, perl, etc.).
  • Understanding the timing closure process (synthesis/STA).
  • Understanding DFT.

Understanding the entire chip development flow.

location – Ramat-Gan

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IT Network Engineer

• Participate in implementation, and support of multiple sites and WAN connectivity.
• Network support during and after hours for local sites and remote sites.
• Troubleshooting end to end connectivity problems, identifying the underlying issues and correcting them.
• Participation in Marvells change control process to document any modifications to the network
• Updating documentation to include diagrams, word documents, monitoring systems and KB’s as they relate to the network
• Responsible for proactive monitoring and maintenance including incident response, upgrades, modifications and improvements within the frame of the Marvell network standards.
• Maintains real-world, working knowledge of network-related technologies.
• Build and maintain excellent relationships with the greater network and IT team, understanding and meeting their requirements.
• Administers support tickets according to established guidelines, standards, and procedures.

דרישות התפקיד

• Experience with Cisco (IOS and NXOS) and Brocade
• Experience with Riverbed WanOpt
• Experience with Cisco ASA or Checkpoint or Palo Alto firewalls is a bonus
• Multi-vendor experience with routing and switching equipment
• Cisco Wireless management and deployment
• Hands on experience with EIGRP, BGP, OSPF
• Experience with networking monitoring tools such as Solarwinds
• Solid troubleshooting and analytical thinking skills
• 4+ years of experience in network implementation and support preferably at the enterprise level
• Excellent communication and documentation skills

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Software methodology & Infrastructure student

Student for EPMI – Embedded Processor Methodology & Infrastructure team.
Be part of group that define and build the tools for all System on a chip group.
The job will include
• Write software for automation of complicated and multi discipliners flow.
• Insert new technologies to emulation system like assertions, scheduler.
• Define, write and assimilate new tools and methodologies. 1. Computer science or computer Eng.
2. Second year and up or previous knowledge in C & C++.
3. C & C++ knowledge – advantage.

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מהנדסי חומרה

Design team manager

A Team manager in the Switch IP department manages 2-6 engineers, including their task allocations, schedule, work effectiveness, acquiring technical skills, career development, and more.

The team manager is responsible for several units or cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification environment, managing the full development flow and manage external interfaces.

The team manager is responsible for the team schedule and meeting quality for the different project milestones.

Required skills and experience:

  • 8+ years’ experience in VLSI development
  • Hands-on experience in design and verification
  • Team management experience
  • Excellent personal skills
  • Visionary and strategic
  • High motivation and desire to influence
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מהנדסי חומרה

IP Engineering Program Manager

Description

Marvell Networking is cutting edge silicon technology team, delivering some of the most complex products in the semiconductor industry.
We’re looking for a person that will join our team and be directly responsible for flawless delivery of complex analog IPs and new package technologies into our various Networking products.
You will own the IP program from definition to production, driving and coordinating between IP vendors, technical experts within the team, architecture team, program execution team & operations.
You will manage the communication with the IP vendor – bringing SoWs & special NDAs to completion, overlooking schedule and quality of delivery – making sure vendors meet their commitment on time.
You will make tradeoffs, resolve conflicts, mitigate risks, challenge & push the team to deliver best possible products.
Qualifications
3-5 years of technical project/program management in chip/analog development
Outstanding communication and presentation skills
Strong technical proficiency with lot of chip flow background mainly in physical & post silicon
Technical knowledge in circuit & package
Deep understanding in managing IP vendors delivery
Independent and Self-directed
Education – BSc in Electrical Engineering

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Associate Design and Verification Student

Description

Marvell Israel is searching for highly potential and motivated student to join to the professional DFT (Design for Test) team that is addressing hi-scale next generation projects. Will be asked for advanced design and verification related activities while working with the most advanced commercial Electronic Design Automation (EDA) vendors and Tools for meeting Marvell hi-end standards. Asking for high technical skills and innovative thinking, when working on advance and complex top of technology devices, infrastructure, flows and tools.

Qualifications
2nd / 3rd year student in EE (must)
• Excellent interpersonal and communication skills (must)
• Self-managed , Independent work capabilities and good learning skills (must)
• Innovative thinking (must)
• Highly technical and analytical capabilities (must)
• Knowledge with logic design and verification (advantage)
• Knowledge in programming languages Verilog, VHDL, C/C++ , TCL (advantage)
• Experience with workflow and automation infrastructure development (advantage)
• Experience with commercial Electronic Design Automation (EDA) vendors and Tools (advantage)

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Architectural Exploration and Modeling student

The requisition is for an intern position in the switching architecture group

• We are developing innovative architectures that require deep architecture exploration.

• Simulation models are the main tools for exploring new architectures, validating them in context of the device level and at system level. At device level the simulations models provide means for analysis of Architectural and uArchitectural alternatives, SW/HW tradeoffs. At system level, the simulation models enable exploring system level feature for example: network caching and dynamic load balancing algorithms.

The activity is partitioned to two stages:

• Development of simulation models and infrastructure at device level and system level (e.g. Data Center). This includes traffic generators, abstract system nodes and specific device level mechanisms and features. C/C++ knowledge is an advantage but not mandatory.

• Architecture exploration which involves running regressions of different architecture options and parameters, analysis of simulation metrics leading to recommendations for the architecture.

The intern will develop simulation models at device level and system level based on tools like C++ and SystemC. The models will be used for architecture exploration. The definition might be in different levels of details – either as a fully detailed specification that needs implementation or at higher level problem statement that requires the candidate to develop a solution.

In any case – it is expected from the candidate to fully understand the architecture being explored and the results of the simulation in order to fix/improve the solution.

Education: 3rd year student for BSC in electrical or computer engineering

Skills:

• Programming – Advantage

o C/C++, SystemC, Perl, Python scripting

• Knowledge – Advantage

o Computer architecture

o Networking

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מהנדסי חומרה

Design Engineering Leader

Description

Be part of a Highly skilled, energetic team developing the next generation high – end Embedded SOCs and Communication SOCs for the networking industry.
Lead a team of logic designers through simulation, documentation and SoC integration.
Perform Micro-architectures
Design/develop custom modules.
Interact with IP teams/vendors to resolve all technical implementation and integration issues.
Work closely with other Design/DV/Validation/SW teams
Work closely with Synthesis, STA and PD teams towards Layout and Timing closure.
Qualifications
B.Sc. in Electrical Engineering
At least 5+ experience years in Design aspects, flows, methodologies and tools.
Good learning and personal skills.
Problem-solving skills
Leading skills
Leading experience – Advantage

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