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מהנדסי חומרה

Formal Verification Engineer -180387

Description

As a member of the Formal-Verification team you will participate in the FV efforts for Marvell's next generation IPs. This team is focusing on working with RTL designers, executing FV methodologies using the industry’s best FV tools.

You will be responsible to adjust the FV work to the right design, and to execute the FV plan, proving the design.

Qualifications 

• Familiar and capable of logic reasoning

• Knowledge of FV practice

• Ability to lead (technical wise) FV methodologies

• Ability to work independently with logic designer

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מהנדסי חומרה

Senior Asic Design and Verification Engineer-171925

Description

Emerging SoC Technologies and Markets department is responsible for the development of NVMf technology for next generation of networking storage products.

Team had been working on the 1st NVMf generation, ownership include architecture, definition and implementation of cores IPs – RDMA and NVU.

we are Seeking an experienced ASIC Verification Engineer with proven analytical and technical skills for verification of next generation storage networking ASICs. This is an excellent opportunity to be part of an startup-like team with big company umbrella.

RESPONSIBILITIES

  • Design Micro-architecture & Documentation
  • Verification Micro-architecture & Documentation
  • Verification environment, coding, and test writing
  • System testing and debug using FPGAs is an advantage
  • Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
  • Scripting

Qualifications

  • 5-10 years’ experience in verification of networking ASICs
  • Strong communication skills, both verbal and written
  • Proficiency with Verilog & System Verilog
  • Proficiency with UVM strongly desired
  • Experience in architecting test bench environments for unit and system level verification
  • Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe
  • Proven track record with writing detailed test plans
  • Problem solving skills and out-of-the-box thinking to test and validate RTL
  • Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
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מהנדסי חומרה

Senior Architect Engineer-180284

Description

Marvell  is Looking for an architect position to focus on physical layer aspects of switching systems. Responsible of the definition of the products architecture (HW, FW,SW) to address high speed interconnect, 802.3 L1/L2 and system level design aspects (thermal, mechanical, bom)
Qualifications
deep understanding of very high speed interconnect interfaces (SERDES) broad understanding of switching systems design in terms of power, thermal, signal integrity mechanics , build of material and cost Need to be very knowledgeable in Ethernet standards IEEE802.3

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מהנדסי חומרה

Chip Design Technical leader-180123

Description

Marvell Israel is searching Experience design engineer for unit and top level design and infrastructures development and lead.  Joining to the professional (Design for Test) team that is addressing hi-scale next generation projects and infrastructure on advanced DFT, Clocks, Reset, Power areas.
Working with the most advanced design flows, commercial Electronic Design Automation (EDA) and in-house design infrastructure for meeting Marvell hi-end ATPG requirements.  Asking for high technical skills and experience with design flows and timing/sdc/lint/power aspects , innovative thinking, excellent interpersonal skills and leading abilities when working on advance and complex top of technology devices and infrastructure/flows/tools.
Responsibilities will include:
– Advanced Top and IP design definition , implementation and leading
– DFT, Power, Area and Timing  design and infrastructure development
– Technical design lead for end to end solution with variant work interfaces
Qualifications
• BsC  in Electrical Engineering
• 8+ Years’ experience  in Logic Design and related aspects (SDC, Power ,Clocks & Resets)
• Proven independent design experience  with IP/Chip design logic
• Design to Backend implementation (synthesis , place and route)
• High level problem solving skills
• Technical leading abilities
• Excellent interpersonal and communication  skills
• Power, DFT (Design for Test) and ATPG experience – an advantage
• Experience with infrastructure development – an advantage

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מהנדסי חומרה

IP Engineering Program Manager-180097

Description

Marvell Networking is cutting edge silicon technology team, delivering some of the most complex products in the semiconductor industry.
We’re looking for a person that will join our team and be directly responsible for flawless delivery of complex analog IPs and new package technologies into our various Networking products.
You will own the IP program from definition to production, driving and coordinating between IP vendors, technical experts within the team, architecture team, program execution team & operations.
You will manage the communication with the IP vendor – bringing SoWs & special NDAs to completion, overlooking schedule and quality of delivery – making sure vendors meet their commitment on time.
You will make tradeoffs, resolve conflicts, mitigate risks, challenge & push the team to deliver best possible products.
Qualifications
3-5 years of technical project/program management in chip/analog development
Outstanding communication and presentation skills
Strong technical proficiency with lot of chip flow background mainly in physical & post silicon
Technical knowledge in circuit & package
Deep understanding in managing IP vendors delivery
Independent and Self-directed
Education – BSc in Electrical Engineering

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מהנדסי תוכנה

Chip Validation Team Leader -172140

Description

• Lead a team of Post Silicon, System and unit level validation.
• Lead a team that Develops and executes Validation automation suites
• Debug Chip functionality – Hardware and Software drivers
• Complex Lab environment of state-of-the-art test equipment’s
• Multiple Environments: Working on target, On simulations, On FPGA and on Emulator as well as reference design and customer boards
• Working closely with other Disciplines and partners as Silicon Design, Software, Hardware, Applications and Architecture
Qualifications
• 4+ years of experience in chip verification/validation with software background
• Deep technical skills and experience in the lab.
• Leadership and management skills.
• Experience in Networking industry
• Hands-on experience with Lab & Test tools
• Validation methods (Test Plan, Test Strategy)
• Python Scripts and automation environments
• Good interpersonal and communication skills, both verbal and written.
• BSc degree in Electrical Engineering / Computer Engineering / Computer Science

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מהנדסי חומרה

Senior Design and Verification Engineer-171438

Description

The engineer will take ownership over a unit or several units. He will do unit level design and verification and will plan and execute the verification. He will also participate in the cluster level verification.

The engineer will work with architects to understand and influence the unit architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until quality criteria is met.

Qualifications

  • Electrical engineering B.Sc graduate
  • Design RTL experience in Verilog or SV
  • Verification experience in SV, UVM, perl,
  • Knowledge in programming
  • Good learning skills
  • Problems solving skill
  • Ability to be a part of a team, working in cooperation
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מהנדסי חומרה

Senior Verification Engineer-171155

Description  

•Design Micro-architecture & Documentation
• Verification Micro-architecture & Documentation
• Verification environment, coding, and test writing
• System testing and debug using FPGAs is an advantage
• Debugging (e.g. PCIe, Network Protocol and Logic Analyzers)
• Scripting
Qualifications
• 7 or more years’ experience in verification of networking ASICs
•Strong communication skills, both verbal and written
• Proficiency with Verilog & System Verilog
• Proficiency with UVM strongly desired
• Experience in architecting test bench environments for unit and system level verification
• Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe
• Proven track record with writing detailed test plans
• Problem solving skills and out-of-the-box thinking to test and validate RTL
• Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis

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Associate Design and Verification Engineer-171118

Description

Marvell Israel is searching for highly potential and motivated student to join to the professional DFT (Design for Test) team that is addressing hi-scale next generation projects.

Will be asked for advanced design and verification related activities while working with the most advanced commercial Electronic Design Automation (EDA) vendors and Tools for meeting Marvell hi-end standards.

Asking for high technical skills and innovative thinking, when working on advance and complex top of technology devices, infrastructure, flows and tools

Qualifications

  • • 2nd / 3rd year student in EE • Excellent interpersonal and communication skills • Knowledge with logic design and verification (advantage) • Knowledge in programming languages Verilog, VHDL, C/C++ , TCL (advantage) • Experience with workflow and automation infrastructure development (advantage) • Experience with commercial Electronic Design Automation (EDA) vendors and Tools (advantage)
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מהנדסי חומרה

Senior Backend Engineer-180130

Description
We are seeking a talented Back-end Team member to join our Embedded CPU division at Marvell Israel
This division develops some of the most advanced, high performance Arm-based Systems on chip in the industry.
In this role you will join a strong and growing Backend team, work with sophisticated tools and flows.
You will be working on industry’s most advanced projects, coping with challenges in timing closure, area reduction & power optimization.
Also, you will be working at advanced technology nodes, 28nm, 16nm, 12nm, deploying Synopsys/Cadence flows, using internally developed flows
Through this role you will have close interaction with Design, DFT and Layout teams.
Qualifications
B.Sc. or MSc in Electrical Engineering
3+ years in Back-end design in advanced technology nodes with either Synopsys or Cadence tools
Deep knowledge in Back-end flows RTL-GDSII, Physical Synthesis, Floorplan, P&R, CTS, STA and Power Analysis
Scripting & Programming skills in Perl and TCL.
RTL/DFT Design background – advantage
Advanced process experience (16nm/12nm) – advantage
Good inter personal relationship and should be able to work in a team and be a good team player.

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