בואו לעבוד איתנובואו למצוא את המשרה שתתאים לכישוריכם האישיים ולשאיפות המקצועיות שלכם
Staff Software Engineer
Be involved in a key position writing SW for MTS products
Design and coding, in C, of a Hardware abstract layer.
Bring-up and support for new PHY and packet processors
Design and implement both low and high level networking applications and protocols.
BA/BSC in Computer Science/SW Engineering /Electrical Engineering
3 or more years of experience in development for embedded systems – Must.
Skilled Developer in ANSI-C – Must.
Networking – Advantage.
Linux – Advantage.
Scrum/Agile – Advantage.
SW associated engineer
Software driver and applications development for Real-time Embedded systems.
Systems are related to Ethernet bridges and routers.
Design, development and testing of different parts of the driver and other layers.
Student in SW Engineering or Computer Science
At least 1.5 years till graduation
Quick learning ability
C programming language is must.
Linux, Windows environment for development and target platforms.
Position located in Petach Tikva
Associate VLSI Design engineer
Be part of a Highly skilled, energetic team developing the next generation high – end Embedded SOCs and Communication SOCs for the networking industry.
Be part of Verification Definition and Implementation.
Interact with IP teams/vendors to resolve all technical verification issues.
Work closely with Design/DV/Validation/SW teams.
B.Sc. student in Electrical/SW Engineering in one of Israel’s leading universities
Hunger to learn and be part of a fast moving engineering team.
Senior Design Engineer
You will join the Full Chip Design Team as a Full Chip Integration Design Engineer.
Your daily tasks will include:
• Work with PD and ARC teams get the definition for the device, write the Arc and implement the needed design.
• Gain system understanding and knowledge in the switch architecture
• Work with the different IP teams, get their deliveries and integration guide line and implement it
• Learning internal integration tools and use it for chip integration and macro partitioning
• Work with FC teams and customers (Verification, emulation, BE) to get their requirements and support their needs.
• Ability to support the BE team with timing analysis and floor plan adjustments
• Knowledge in Verilog and System Verilog
• System view oriented – manages to see the full picture
• Integration experience – advantage
• Good understanding of Networking and the switching packet walk through – advantage
• I/O and package knowledge – advantage
• Experience in design IP or Full chip of at least 5 to 8 years
• Good debug capabilities
• Complex situation handling – time management and priority management
• Team work oriented – Communicative, shares his knowledge and will to learn from others, good personal relation and working relation in a team.
• Independent Quality driven – understands the definition, drive high quality and ability for self-check
• Stability – willing to invest for long period
Full chip verification staff engineer/leader
Experience with SV/UVM/C++ verification environments
Experienced in unit level verification
Experienced in FC/system level verification
Good architectural understanding
Excellent interpersonal skills
BSC in EE or CS
Knowledge in advanced verification methodologies (UVM/ Specman)
Experienced in unit level verification
Experienced in full chip verification
Deep understanding of modern verification concepts
Good debug capabilities
Knowledge in networking – advantage
Excellent interpersonal skills
Experienced PCIE Engineer
We are seeking a PCIE expert with proven analytical and technical skills for design and verification of PCIE for next generation switching ASICs.
You will join to the switching chip design team which is responsible for the projects execution and be the PCIE focal point of the group.
Daily tasks include:
Gain system understanding and knowledge in the PCIE standard.
Work with Product Definition and Architecture teams, get the PCIE definition for the device and implement the needed design.
Run Unit Level verification.
Support the BE team with timing analysis, SDC guideline and reviews.
Guide the project with PCIE integration and support Full Chip verification team.
Responsible to perform Post Silicon debug of PCIE.
Handling the legal department administrative and legal tasks such as: • Corporate filings • Legal contract archive administrator • legal research and drafting of legal opinions • Outside attorney fees • Letter drafting • Review of NDA’s and license agreements
• 2nd year law student • Estimated graduation not earlier than August 2019 • High academic grades • High level in English (read and write) • Fluent Hebrew • Good organization skills, ability for self-learning • 3 days a week (around 20 hours) – subject to academic constraints • Good interpersonal skills, able to multi task and work under pressure • Flexible hours
HW Validaon Engineer
Switching Platform HW group, HW validation – System level Stress Test for Switching products at MIS Yokneam HW lab. Main duties:
Stress Test station system build: interconnect, DB, cooling / heating, SW Rev.
Test coding and parameterizing, setting and implementing the test concept and test list, test code at C/Python environment.
Test execution, results analysis, and debug. Problems localization.
Work interfaces: HW project leader, Platform SW, CV, Apps, Design team, Program Manager.
BSC in Electrical Engineering or in Computer Science
3-8 years’ experience in high speed digital board design, in System or Electrical testing / Validation, and with practical Lab working experience.
Working experience in C, C++ and Python programming
Working knowledge in board design: schematic capture tools, layout tools and FPGA design tools.
Strong lab skills with hands on experience, in system bring up, system testing and debug. Networking systems experience – advantage, Electrical test equipment experience (high speed oscilloscopes, spectrum analyzer, VNA, High Speed Ethernet Traffic generator) – advantage
Position located in Yokneam
Design and verification team manager
A Team Leader in the Switch IP department manages 2-6 engineers, including their task allocations, schedule, work effectiveness, acquiring technical skills, career development, and more.
The team leader manages several units or cluster, with good knowledge of the architecture, responsible for choosing correct architecture solutions, planning micro-arch, managing implementation of design and verification environment, managing and responsible for the full development flow and manage external interfaces. Also responsible for the team schedule and meeting quality for the different project milestones.
7 or more years’ experience in verification of networking ASICs • Strong communication skills, both verbal and written • Proficiency with Verilog & System Verilog • Proficiency with UVM strongly desired • Experience in architecting test bench environments for unit and system level verification • Strong protocol knowledge in one or more of the following areas: TCP/IP, Ethernet, RDMA, NVMe, NVMf, SATA protocols, and PCIe • Proven track record with writing detailed test plans • Problem solving skills and out-of-the-box thinking to test and validate RTL • Team-Player, can-do attitude and will work well in a group environment while still being able to contribute on an individual basis
Senior Design and Verification engineer
The engineer will take ownership over a unit or several units. He will do unit level design and verification and will plan and execute the verification. He will also participate in the cluster level verification.
The engineer will work with architects to understand and influence the unit architecture, plan and implement design changes in Verilog or SV, plan and implement verification environment in UVM, and execute the verification plan until quality criteria is met.
Electrical engineering B.Sc graduate
4+ years’ experience in VLSI development
Design RTL experience in Verilog or SV
Verification experience in SV, UVM, perl,
Knowledge in programming
Good learning skills
Problems solving skill
Ability to be a part of a team, working in cooperation
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